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ar0130cs: 1/3-inch cmos digital image sensor features ? ar0130cs/d rev. 12, 1/16 en 1 ?semiconductor components industries, llc 2016. 1/3-inch cmos digital image sensor ar0130cs datasheet, rev. 12 for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance both in vga mode and hd mode ? excellent near ir performance ? hd video (720p60) ? on-chip ae and statistics engine ? auto black level calibration ?context switching ?progressive scan ? supports 2:1 scaling ? internal master clock generated by on-chip phase locked loop (pll) oscillator. ? parallel output applications ? gaming systems ? video surveillance ? 720p60 video applications general description on semiconductor's ar0130 is a 1/3-inch cmos digi- tal image sensor with an ac tive-pixel array of 1280h x 960v. it captures images with a rolling-shutter readout. it includes sophisticated camera functions such as auto exposure control, windowing, and both video and single frame modes. it is programmable through a sim- ple two-wire serial interf ace. the ar0130 produces extraordinarily clear, sharp digital pictures, and its ability to capture both co ntinuous video and single frames makes it the perfect choice for a wide range of applications, including gaming systems, surveillance, and hd video. table 1: key parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280 x 960 = 1.2 mp pixel size 3.75 ? m color filter array monochrome, rgb bayer shutter type electronic rolling shutter input clock range 6 C 50 mhz output clock maximum 74.25 mhz output parallel 12-bit max. frame rates 1.2 mp (full fov) 45 fps 720phd (reduced fov) 60 fps vga (full fov) 45 fps vga (reduced fov) 60 fps 800 x 800 (reduced fov) 60 fps responsivity at 550 nm (mono) 6.5 v/lux-sec responsivity at 550 nm (rgb green) 5.6 v/lux-sec snr max 44 db dynamic range 82 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v power consumption 270 mw (1280x720 60 fps) operating temperature C30c to + 70c (ambient) C30c to + 80c (junction) package option bare die, ilcc, plcc
ar0130cs/d rev. 12, 1/16 en 2 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. fo r reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number base description variant description ar0130cssc00spba0-dp1 rgb bayer 48-pin plcc dry pack with protective film ar0130cssc00spba0-dr1 rgb bayer 48-pin plcc dry pack without protective film ar0130cssc00spca0-dpbr1 rgb bayer 48-pin ilcc dry pack with protective f ilm, double side bbar glass ar0130cssc00spca0-drbr1 rgb bayer 48-pin ilcc dry pack without protective f ilm, double side bbar glass ar0130cssc00spcad3-gevk rgb bayer demo kit ilcc ar0130cssc00spcad3-s115-gevk rgb bayer demo kit ilcc ar0130cssc00spcad3-s213a-gevk rgb bayer demo kit ilcc ar0130cssc00spcad-gevk rgb bayer demo kit ilcc ar0130cssc00spcad-s115-gevk rgb bayer demo kit ilcc ar0130cssc00spcad-s213a-gevk rgb bayer demo kit ilcc ar0130cssc00spcah-gevb rgb bayer headboard ilcc ar0130cssc00spcah-s115-gevb rgb bayer headboard ilcc ar0130cssc00spcah-s213a-gevb rgb bayer headboard ilcc ar0130cssc00spcaw-gevb rgb bayer headboard ilcc ar0130cssm00spca0-drbr1 monochrome 48-pin ilcc dry pack without protective f ilm, double side bbar glass ar0130cssm00spcad-s213a-gevk monochrome demo kit ilcc ar0130cssm00spcah-s213a-gevb monochrome headboard ilcc
ar0130cs/d rev. 12, 1/16 en 3 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 real-time context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
ar0130cs/d rev. 12, 1/16 en 4 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor general description general description the on semiconductor ar0130 can be operated in its default mode or programmed for frame size, exposure, gain, and other parame ters. the default mode output is a 960p- resolution image at 45 frames per second (f ps). it outputs 12-bit raw data over the parallel port. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are ou tput on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0130 includes additional features to allow application-specific tuning: windowing and offset, adjustable auto-exposur e control, and auto bl ack level correction. optional register information and histogra m statistic information can be embedded in first and last 2 line s of the image frame. functional overview the ar0130 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 mhz the maximum output pixel rate is 74.25 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is throug h the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.2 mp active- pi xel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correct ion and gain), and then through an analog- to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which control registers active pixel sensor (aps) array pll memory otpm timing and control (sequencer) analog processing and a/d conversion auto exposure and stats engine pixel data path (signal processing) external clock parallel output two-wire serial interface trigger power
ar0130cs/d rev. 12, 1/16 en 5 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor functional overview provides further data path corrections and applies digital gain). the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and line synchronization signals. figure 2: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. on semiconductor recommends that vdd_slvs pad (o nly available in bare di e) is left unconnected. 5. on semiconductor recommends that 0.1f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay- out and design considerations. check the ar01 30 demo headboard schematics for circuit recom- mendations. 6. on semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 7. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. v dd master clock (6C50 mhz) s data s clk reserved frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, 3 v aa v aa _pix analog power 1 vdd_pll pll power 1 analog power 1 v aa _pix v dd _io v dd _pll v dd v aa trigger oe_bar standby a gnd s addr
ar0130cs/d rev. 12, 1/16 en 6 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor functional overview table 3: pad descriptions name type description standby input standby-mode enable pin (active high). v dd _pll power pll power. v aa power analog power. extclk input external input clock. v dd _slvs power digital po wer (do not connect). d gnd power digital ground. v dd power digital power. a gnd power analog ground. s addr input two-wire serial interface address select. s clk input two-wire serial interface clock input. s data i/o two-wire serial interface data i/o. v aa _pix power pixel power. line_valid output asserted when d out line data is valid. frame_valid output asserted when d out frame data is valid. pixclk output pixel clock out. d out is valid on rising edge of this clock. v dd _io power i/o supply power. d out 8 output parallel pixel data output. d out 9 output parallel pixel data output. d out 10 output parallel pixel data output. d out 11 output parallel pixel data output (msb) reserved input connect to d gnd . d out 4 output parallel pixel data output. d out 5 output parallel pixel data output. d out 6 output parallel pixel data output. d out 7 output parallel pixel data output. trigger input exposure synchronization input. oe_bar input output enable (active low). d out 0 output parallel pixel data output (lsb) d out 1 output parallel pixel data output. d out 2 output parallel pixel data output. d out 3 output parallel pixel data output. reset_bar input asynchronous reset (active low). a ll settings are restored to factory default. flash output flash control output. nc input do not connect.
ar0130cs/d rev. 12, 1/16 en 7 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor functional overview figure 3: 48-pin ilcc pinout diagram 1 2 3 4 5 6 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 d out 7 d out 8 d out 9 d out 10 d out 11 v dd _io pixclk v dd s clk s data reset_bar v dd _io nc nc v aa a gnd v aa _pix v aa _pix v aa a gnd v aa nc nc nc v dd nc nc standby oe_bar s addr reserved flash trigger frame_valid line_valid d gnd d gnd extclk v dd _pll d out 6 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 d gnd nc 48 47 46 45
ar0130cs/d rev. 12, 1/16 en 8 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor functional overview figure 4: 48-pin plcc pinout diagram top view reserved oe_bar nc nc nc reset_bar v dd _io v dd _io v dd v dd _pll v dd v dd v aa _pix v aa _pix v aa v aa v aa s clk s addr s data d gnd d gnd d gnd a gnd a gnd a gnd a gnd a gnd a gnd d out 9 d out 8 d out 7 d out 6 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 d out 11 d out 10 trigger extclk pixclk flash frame_valid line_valid standby
ar0130cs/d rev. 12, 1/16 en 9 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor pixel data format pixel data format pixel array structure the ar0130 pixel array is configured as 1412 columns by 1028 rows, (see figure 5). the dark pixels are optically black and are used internally to monitor black level. of the right 108 columns, 64 are dark pixels used for ro w noise correction. of the top 24 rows of pixels, 12 of the dark rows are used for bl ack level correction. there are 1296 columns by 976 rows of optically active pixels. while the sensor's format is 1280 x 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow re adout to start on the same pixel. the pixel adjustment is always performed for monochrome or color ve rsions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. figure 5: pixel array description 2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy dark pixel barrier pixel light dummy pixel active pixel 2 light dummy + 4 barrier + 6 dark dummy 1412 2 light dummy + 4 barrier 2 light dummy + 4 barrier + 100 dark + 4 barrier 1028 1296 x 976 (1288 x 968 active) 4.86 x 3.66 mm 2 (4.83 x 3.63 mm 2 )
ar0130cs/d rev. 12, 1/16 en 10 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor pixel data format figure 6: pixel color patt ern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 6). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (112, 44). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 7. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced as shown in figure 7 on page 10. figure 7: imaging a scene active pixel (0,0) array pixel (112, 44) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction lens pixel (0,0) row readout order column readout order scene sensor (rear view)
ar0130cs/d rev. 12, 1/16 en 11 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor output data format output data format the ar0130 image data is read out in a progressive scan. valid image data is surrounded by horizontal and vertical blan king (see figure 8). the amount of horizontal row time (in clocks) is programmable thro ugh r0x300c. the amount of ve rtical frame time (in rows) is programmable through r0x300a. line_valid (lv) is high during the shaded region of figure 8. optional embedded register se tup information and histogram statistic information are available in firs t 2 and last row of image data. figure 8: spatial illust ration of image readout readout sequence typically, the readout window is set to a region including only active pixels. the user has the option of reading out dark regions of the a rray, but if this is done, consideration must be given to how the sensor reads th e dark regions for its own purposes. p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
ar0130cs/d rev. 12, 1/16 en 12 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor output data format parallel output data timing the output images are divided into frames, which are further divided into lines. by default, the sensor produces 968 rows of 1 288 columns each. the fv and lv signals indi- cate the boundaries between frames and lines, respectively. pixclk can be used as a clock to latch the data. for each pixclk cycle, with respect to the falling edge, one 12-bit pixel datum outputs on the d out pins. when both fv and lv are asserted, the pixel is valid. pixclk cycles that occur when fv is de-asserted are called vertical blanking. pixclk cycles that occur when only lv is de-asserted are called horizontal blanking. figure 9: default pixel output timing lv and fv the timing of the fv and lv outputs is closely related to the row time and the frame time. fv will be asserted for an integral number of row times, which will normally be equal to the height of the output image. lv will be asserted during the valid pixels of each row. the leading edge of lv will be offset from the leading edge of fv by 6 pixclks. normally, lv will only be asserted if fv is asserted; this is configurable as described below. lv format options the default situation is for lv to be de-asse rted when fv is de-asserted. by configuring r0x306e[1:0], the lv signal can take two different output formats. the formats for reading out four lines and two vertical blanking line s are shown in figure 10. figure 10: lv format options the timing of an entire frame is shown in figure 11: ?line timing and frame_valid/ line_valid signals,? on page 13. pixclk fv lv d out [11:0] p0 p1 p2 p3 p4 pn vertical blanking horiz blanking valid image data horiz blanking vertical blanking default continuous lv fv lv fv lv
ar0130cs/d rev. 12, 1/16 en 13 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor output data format frame time the pixel clock (pixclk) represents the time needed to sample 1 pixel from the array. the sensor outputs data at the maximum ra te of 1 pixel per pixclk. one row time ( t row) is the period from the first pixel output in a row to the first pixel output in the next row. the row time and frame time are defined by equations in table 4. figure 11: line timing and frame_valid/line_valid signals sensor timing is shown in terms of pixel clock cycles (see figure 8 on page 11). the recommended pixel clock frequency is 74.25 mhz. the vertical blanking and the total frame time equations assume that the integrat ion time (coarse integration time plus fine integration time) is less than the number of active lines plus the blanking lines: window height + vertical blanking (eq 1) if this is not the case, the number of integration lines must be used instead to determine the frame time, (see table 5). in this example, it is assumed that the coarse integration time control is programmed wi th 2000 rows and the fine shutter width total is zero. for master mode, if the integration time registers exceed the total readout time, then the vertical blanking time is internally extended automatica lly to adjust for the additional integration time required. this extended value is not written back to the frame_length_lines register. the frame_length_lines register can be used to adjust frame-to-frame readout time. this register does not affect the exposure time but it may extend the readout time. table 4: frame time (example based on 1280 x 960, 45 frames per second) parameter name equation timing at 74.25 mhz a active data time context a: r0x3008 - r0x3004 + 1 context b: r0x308e - r0x308a + 1 1280 pixel clocks = 17.23 ? s p1 frame start blanking 6 (fixed) 6 pixel clocks = 0.08 ? s p2 frame end blanking 6 (fixed) 6 pixel clocks = 0.08 ? s q horizontal blanking r0x300c - a 370 pixel clocks = 4.98 ? s a+q (trow) line (row) time r0x300c 1650 pixel clocks = 22.22 ? s v vertical blanking context a: (r0x300a-(r0x3006-r0x3002+1)) x (a + q) context b: ((r0x30aa-(r0x3090-r0x308c+1)) x (a + q) 49,500 pixel clocks = 666.66 ? s nrows x (t row ) frame valid time context a: ((r0x3006-r0x3002+1)*(a+q))-q+p1+p2 context b: ((r0x3090-r0x308c+1)*(a+q))-q+p1+p2 1,583,642 pixel clocks = 21.33ms f total frame time v + (nrows x (a + q)) 1,633,500 pixel clocks = 22.22ms p1 a q a q a p2 number of pixel clocks frame_valid line_valid ... ... ...
ar0130cs/d rev. 12, 1/16 en 14 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor output data format note: the ar0130 uses column para llel analog-digital converters; thus short line timing is not possible. the minimum total line time is 1390 columns (hor izontal width + horizontal blanking). the mini- mum horizontal blanking is 110. exposure total integration time is the result of co arse_integration_time and fine_integration_- time registers, and depends also on whether manual or automatic exposure is selected. the actual total integration time, t int is defined as: t int = t intcoarse - 410 - t intfine (eq 2) = (number of lines of integration x line time) - (410 pixel clocks of conversion time over- head) - (number of pixels of integration x pixel time) where: ? number of lines of integration (auto exposure control: enabled) when automatic exposure control (aec) is enabled, the number of lines of integra- tion may vary from frame to frame, with the limits controlled by r0x311e (mini- mum auto exposure time) and r0x311c (maximum auto exposure time). ? number of lines of integration (a uto exposure control: disabled) if aec is disabled, the number of lines of integration equals the value in r0x3012 (context a) or r0x3016 (context b). ? number of pixels of integration the number of fine shutter width pixels is independent of aec mode (enabled or disabled): ? context a: the number of pixels of integration equals the value in r0x3014. ? context b: the number of pixels of integration equals the value in r0x3018. typically, the value of the coarse_integration_ time register is limited to the number of lines per frame (which includes vertical blanking li nes), such that the frame rate is not affected by the integration time. for more information on coarse and fine integration time settings li mits, please refer to the register reference document. table 5: frame time: long integration time parameter name equation (number of pixel clock cycles) default timing at 74.25 mhz f total frame time (long integration time) context a: (r0x3012 x (a + q)) + r0x3014 + p1 + p2 context b: (r0x3016 x (a + q)) + v r0x3018 + p1 + p2 3,300,012 pixel clocks = 44.44ms
ar0130cs/d rev. 12, 1/16 en 15 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor real-time context switching real-time context switching in the ar0130, the user may switch between two full register sets (listed in table 6) by writing to a context switch change bit in r0 x30b0[13]. this context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time. features see the ar0130 register refere nce for additional details. reset the ar0130 may be reset by using reset_ba r (active low) or the reset register. hard reset of logic the reset_bar pin can be connected to an external rc circuit for simplicity. the recommended rc circuit uses a 10k ? resistor and a 0.1 ? f capacitor. the rise time for the rc circuit is 1 ? s maximum. soft reset of logic soft reset of logic is controlled by the r0x 301a reset register. bit 0 is used to reset the digital logic of the sensor while preserving th e existing two-wire se rial interface configu- ration. furthermore, by assertin g the soft reset, the sensor aborts the current frame it is processing and starts a new fram e. this bit is a self-resetting bit and also returns to ?0? during two-wire seri al interface reads. clocks the ar0130 requires one clock input (extclk). table 6: real-time context-switchable registers register description register number context a context b y_addr_start r0x3002 r0x308c x_addr_start r0x3004 r0x308a y_addr_end r0x3006 r0x3090 x_addr_end r0x3008 r0x308e coarse_integration_time r0x3012 r0x3016 fine_integration_time r0x3014 r0x3018 y_odd_inc r0x30a6 r0x30a8 green1_gain (greenr) r0x3056 r0x30bc blue_gain r0x3058 r0x30be red_gain r0x305a r0x30c0 green2_gain (greenb) r0x305c r0x30c2 global_gain r0x305e r0x30c4 analog gain r0x30b0[5:4] r0x30b0[9:8] frame_length_lines r0x300a r0x30aa digital_binning r0x3032[1:0] r0x3032[5:4]
ar0130cs/d rev. 12, 1/16 en 16 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features pll-generated master clock the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and two divide r stages to generate the output clock. the clocking structure is shown in figure 12. pl l control registers can be programmed to generate desired master clock frequency. note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming th e pll divisors while the sensor is in the streaming state is undefined. figure 12: pll-generated master clock pll setup the pll is enabled by default on the ar0130. to configure and use the pll: 1. bring the ar0130 up as normal; make sure that f extclk is between 6 and 50mhz and ensure the sensor is in software standby (r0x301a[2]= 0). pll control registers must be set in software standby. 2. set pll_multiplier, pre_pll_clk_div, vt_sys _clk_div, and vt_pix_clk_div based on the desired input (f extclk ) and output ( f pixclk ) frequencies. determine the m, n, p1, and p2 values to achieve the desired f pixclk using this formula: f pixclk = ( f extclk m) / (n p1 x p2) where m = pll_multiplier (r0x3030) n = pre_pll_clk_div (r0x302e) p1 = vt_sys_clk_div (r0x302c) p2 = vt_pix_clk_div (r0x302a) 3. wait 1ms to ensure that the vco has locked. 4. set r0x301a[2]=1 to enable streaming and to switch from extclk to the pll-gener- ated clock. notes: 1. the pll can be bypassed at any time (sensor will run directly off extclk) by setting r0x30b0[14]=1. however, only the parallel data interface is su pported with the pll bypassed. the pll is always bypassed in software standby mode. to disable the pll, the sensor must be in standby mode (r0x301a[2] = 0) 2. the following restrictions apply to the pll tuning parameters: pre pll div (pfd) pre _p ll _ clk _ div extclk pll multiplier (vco) pll output div 1 sysclk pixclk vt _p ix _ clk _ div vt _ s y s _ clk _ div pll input clock pll output clock pll output div 2 pll_multiplier 32 m 255 ?? 1n 63 ?? 1p116 ??
ar0130cs/d rev. 12, 1/16 en 17 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features additionally, the vco frequency, defined as must be within 384-768mhz and the extclk must be within 2mhz =< f extclk /n <= 24mhz the user can utilize the register wizard t ool accompanying devware to generate pll settings given a supplied input clock and desired output frequency. spread-spectrum clocking to facilitate improved emi performance, the external clock input allows for spread spec- trum sources, with no impact on image qual ity. limits of the spread spectrum input clock are: ? 5% maximum clock modulation ? 35 khz maximum modulation frequency ? accepts triangle wave modulation, as well as sine or modified triangle modulations. stream/standby control the sensor supports two standby modes: ha rd standby and soft standby. in both modes, external clock can be optionally disabled to further minimize power consump- tion. if this is done, then the ?power-u p sequence? on page 44 must be followed. soft standby soft standby is a low power state that is controlled through register r0x301a[2]. depending on the value of r0x301a[4], the sens or will go to standby after completion of the current frame readout (default behavior) or after the completion of the current row readout. when the sensor comes back from soft standby, previously written register settings are still maintained. a specific sequence needs to be followed to enter and exit from soft standby. to enter soft standby: 1. r0x301a[12] = 1 if serial mode was used 2. set r0x301a[2] = 0 3. external clock can be turned off to fu rther minimize power consumption (optional) to exit soft standby: 1. enable external clock if it was turned off 2. r0x301a[2] = 1 3. r0x301a[12] = 0 if serial mode is used 4p216 ?? f vco f extclk m ? n ? =
ar0130cs/d rev. 12, 1/16 en 18 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features figure 13: enter standby timing figure 14: exit standby timing extclk standby fv 50 e xtc l ks r egister writes not valid registerwrites valid sdata 750 e xtc l ks extclk standby fv trigger 10 e xtc l ks 1ms 28 rows + c it r egis ter writes not valid r egis ter writes valid sdata
ar0130cs/d rev. 12, 1/16 en 19 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features hard standby hard standby puts the sensor in lower power state; previously written register settings are still maintained. a specific sequence needs to be followed to enter and exit from hard standby. to enter hard standby: 1. r0x301a[8] = 1 2. r0x301a[12] = 1 if serial mode was used 3. assert standby pin 4. external clock can be turned off to fu rther minimize power consumption (optional) to exit hard standby: 1. enable external clock if it was turned off 2. de-assert standby pin 3. set r0x301a[8] = 0 window control registers x_addr_start , x_addr_end, y_addr_start, and y_addr_end control the size and starting coordinates of the image window. the exact window height and width out of th e sensor is determined by the difference between the y address start and end registers or the x address start and end registers, respectively. the ar0130 allows different window sizes for context a and context b. blanking control horizontal blank and vertical blank times are controlled by the line_length_pck and frame_length_lines registers, respectively. ? horizontal blanking is specified in terms of pixel clocks. it is calculated by subtracting the x window size from the line_length_pck register. the minimum horizontal blanking is 110 pixel clocks. ? vertical blanking is specified in terms of numbers of lines. it is calculated by subtracting the y window size from the frame_length_lines register. the minimum vertical blanking is 26 lines. the actual imager timing can be calculat ed using table 4 on page 13 and table 5 on page 14, which describe the li ne timing and fv/lv signals.
ar0130cs/d rev. 12, 1/16 en 20 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features readout modes digital binning by default, the resolution of the output image is the full width and height of the fov as defined above. the output resolution can be reduced by digital binning. for rgb and monochrome mode, this is set by the register r0x3032. for context a, use bits [1:0], for context b, use bits [5:4]. available settings are: 00 = no binning 01 = horizontal binning 10 = horizontal and vertical binning binning gives the advantage of reducing noise at the cost of reduced resolution. when both horizontal and vertical binning are used, a 2x improvement in snr is achieved therefore improving low light performance bayer space resampling all of the pixels in the fov contribute to th e output image in digital binning mode. this can result in a more pleasing output image with reduced subsamplin g artifacts. it also improves low-light performance. for rgb mode, resampling can be enabled by setting of register 0x306e[4] = 1. mirror column mirror image by setting r0x3040[14] = 1, the readout order of the columns is reversed, as shown in figure 15. the starting color, and therefore the bayer pattern, is preserved when mirroring the columns. when using horizontal mirror mode, the user must retrigger column correction. please refer to the column correction section to see the procedure for column correction retrig- gering. bayer resampling must be enabled, by setting bit 4 of register 0 x 306e[4] = 1. figure 15: six pixels in normal and column mirror readout modes g0[1 1:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] g2[11:0] r2[11:0] g1[11:0] r1[11:0] g0[11:0] r0[11:0] d out [11:0] lv normal readout d out [11:0] reverse readout
ar0130cs/d rev. 12, 1/16 en 21 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features row mirror image by setting r0x3040[15] = 1, the readout order of the rows is reversed as shown in figure 16. the starting bayer color pixel is main tained in this mode by a 1-pixel shift in the imaging array. when using horizontal mi rror mode, the user must retrigger column correction. please refer to the column correction section to see the procedure for column correction retriggering. figure 16: six rows in norm al and row mirror readout modes row0 [11:0] row1 [11:0] row2 [11:0] row3 [11:0] row4 [11:0] row5 [11:0] row5 [11:0] row4 [11:0] row3 [11:0] row2 [11:0] row1 [11:0] row0[11:0] d out [11:0] fv normal readout d out [11:0] reverse readout
ar0130cs/d rev. 12, 1/16 en 22 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is the desired scenario. this is no t always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a ?bubble? in the output rate (that is, the vertical blank increases for one frame) if they are written in video mode, even if the new value would not change the resulting frame rate. the following list shows only a few examples of such registers; a full listing ca n be seen in the ar0130 register reference. ?x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ? line_length_pclk ? coarse_integration_time ? fine_integration_time ? read_mode the size of this bubble is (integration_time t row ), calculating the row time according to the new settings. the coarse_integration_time and fine_integ ration_time fields may be written to without causing a bubble in the output rate under certain circumstances. because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without sp ecial provisions in the hardware. writes to these registers take effect two frames after the frame they are written, which allows the integration time to increase without interrupting the output or producing a corrupt frame (as long as the change in integrat ion time does not affect the frame time). synchronizing register writ es to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on the frame after the one during which they are written. these fields are noted as ?synchronized to frame boundaries? in the ar0 130 register reference. to ensure that a register update takes effect on the next fr ame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. as a special case, in single frame mode, regist er writes that occur after fv but before the next trigger will take effect immediately on th e next frame, as if there had been a restart. however, if the trigger for the next frame occurs during fv, register writes take effect as with video mode. fields not identified as being frame-sync hronized are updated immediately after the register write is completed. the effect of thes e registers on the next frame can be difficult to predict if they affect the shutter pointer.
ar0130cs/d rev. 12, 1/16 en 23 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features restart to restart the ar0130 at any time during the operation of the sensor, write a ?1? to the restart register (r0x301a[1] = 1). this has two effects: first, the current frame is inter- rupted immediately. second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, an d a new frame starts (in video mode). the current row completes before the new frame is started, so the time between issuing the restart and the beginning of the next frame can vary by about t row . image acquisition modes the ar0130 supports two image acquisition mo des: video (also known as master) and single frame. video the video mode takes pictures by scanning th e rows of the sensor twice. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the re set state. the exposure for any row is there- fore the time between the first and second sc ans. each row is exposed for the same dura- tion, but at slightly different point in time, which can cause a shear in moving subjects as is typical with electronic rolling shutter sensors. single frame the single-frame mode operates similar to the video mode. it also scans the rows of the sensor twice, first to reset the rows and se cond to read the rows. unlike video mode where a continuous stream of images are outp ut from the image sensor, the single-frame mode outputs a single frame in response to a high state placed on the trigger input pin. as long as the trigger pin is held in a high state, new images will be read out. after the trigger pin is returned to a low state, the image sensor will not output any new images and will wait for the next high state on the trigger pin. the trigger pin state is detected during the ve rtical blanking period (i.e. the fv signal is low). the pin is level sensitive rather than edge sensitive. as such, image integration will only begin when the sensor detects that the trigger pin has been held high for 3 consecutive clock cycles. during integration time of single-frame mo de and video mode, the flash output pin is at high. continuous trigger in certain applications, multiple sensors need to have their video streams synchronized (e.g. surround view or panorama view applications). the trigger pin can also be used to synchronize output of multiple image sens ors together and still get a video stream. this is called continuous trigger mode. continuous trigger is enabled by holding the trigger pin high. alternatively, the trigger pin can be held high until the stream bit is enabled (r0x301a[2]=1) then can be re leased for continuous synchronized video streaming. if the trigger pins for all connected ar0130 sensors are connected to the same control signal, all sensors will receive the trigger pulse at the same time. if they are configured to have the same frame timing, then the usage of the trigger pin guarantees that all sensors will be synchronized within 1 pixclk cycle if pll is disabled, or 2 pixclk cycles if pll is enabled.
ar0130cs/d rev. 12, 1/16 en 24 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features with continuous trigger mode, the applicatio n can now make use of the video streaming mode while guaranteeing that all sensor outputs are synchronized. as long as the initial trigger for the sensors takes place at the same time, all subsequent video streams will be synchronous. automatic exposure control the integrated automatic exposure control (aec) is responsible for ensuring that optimal settings of exposure and gain ar e computed and updated every other frame. aec can be enabled or disabled by r0x3100[0]. when aec is disabled (r0x3100[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers and th e manual gain value in the gain registers. when aec is enabled (r0x3100[0]=1), the tar get luma value is set by r0x3102. for the ar0130 this target luma has a default value of 0x0800 or about half scale. the exposure control measures current scene luminosity by accumulating a histogram of pixel values while reading out a frame. it then compares the current luminosity to the desired output luminosity. finally, the appr opriate adjustments are made to the expo- sure time and gain. all pixels are used, regardless of color or mono mode. aec does not work if digital binning is enabled. embedded data and statistics the ar0130 has the capability to output imag e data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout: 1. embedded data: if enabled, these are disp layed on the two rows immediately before the first active pixel row is displayed. 2. embedded statistics: if enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. note: both embedded statistics and data must be enabled and disabled together. figure 17: frame format with embedded data lines enabled image register data status & statistics data hblank vblank
ar0130cs/d rev. 12, 1/16 en 25 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features embedded data the embedded data contains the configurat ion of the image being displayed. this includes all register settings used to capt ure the current frame. the registers embedded in these rows are as follows: line 1: registers r0x3000 to r0x312f line 2: registers r0x3136 to r0x31bf, r0x31d0 to r0x31ff note: all undefined registers will have a value of 0. in parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where th e register data will be broken up into 8 msb and 8 lsb. the alignment of the 8-bit data will be on the 8 msb bits of the 12-bit pixel word. for example, of a register value of 0x123 4 is to be transmitted, it will be trans- mitted over 2, 12-bit pixe ls as follows: 0x120, 0x340. the first pixel of each line in the embedded data is a tag value of 0x0a0. this signifies that all subsequent data is 8 bit data aligned to the msb of the 12-bit pixel. the figure below summarizes how the embedded data transmission looks like. it should be noted that data, as shown in figure 1 8, is aligned to the msb of each word: figure 18: format of embedde d data output within a frame the data embedded in these rows are as follows: ?0x0a0 - identifier ? 0xaa0 ? register address msb of the first register ?0xa50 ? register address lsb of the first register ?0x5a0 ? register value msb of the first register addressed ?0x5a0 ? register value lsb of the first register addressed ?0x5a0 ? register value msb of the register at first address + 2 ?0x5a0 ? register value lsb of the register at first address + 2 ?0x5a0 ?etc. {register_ value_lsb} 8'h5a data line 1 data line 2 8'h5a 8'haa {register_ address_msb} 8'ha5 {register_ address_lsb} 8'h5a {register_ value_msb} 8'h5a {register_ value_lsb} data_format_ code =8'h0a 8'haa {register_ address_msb} 8'ha5 {register_ address_lsb} 8'h5a {register_ value_msb} 8'h5a data_format_ code =8'h0a
ar0130cs/d rev. 12, 1/16 en 26 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features embedded statistics the embedded statistics contain frame iden tifiers and histogram information of the image in the frame. this can be used by do wnstream auto-exposure algorithm blocks to make decisions about exposure adjustment. this histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 2 12 , 120 evenly spaced bins for values 2 12 to 2 16 , 60 evenly spaced bins for values 2 16 to 2 20 . the first pixel of each line in the embedded statistics is a tag value of 0x0b0. this signi- fies that all subsequent statistics data is 10 bit data aligned to the msb of the 12-bit pixel. the figure below summarizes how the embedded statistics transmission looks like. it should be noted that data, as shown in fi gure 19, is aligned to the msb of each word: figure 19: format of embedded statistics output within a frame the statistics embedded in these rows are as follows: line 1: ? 0x0b0 - identifier ? register 0x303a - frame_count ? register 0x31d2 - frame id ? histogram data - histogram bins 0-243 line 2: ?0x0b0 (identifier) ?mean ? histogram begin ?histogram end ?low end histogram mean ? percentage of pixels below low end mean ? normal absolute deviation lowendmean [19:10] stats line 1 stats line 2 histogram bin1 [9:0] #words = 10h1ec {2b00, frame _count msb} {2b00, frame _id msb} {2b00, frame _id lsb} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin1 [19:10] data_format_ code =8'h0b #words = 10h1c mean [ 19:10] mean [9:0] hist_begin [19:10] hist_begin [9:10] 8'h07 data_format_ code =8'h0b {2b00, frame _count lsb} 8'h07 histogram bin243 [19:10] histogram bin243 [9:0] 8'h07 hist_end [19:10] hist_end [9:10] lowendmean [9:0] perc_lowend [19:10] perc_lowend [9:0] norm_abs_dev [19:10] lnorm_abs_dev [9:0]
ar0130cs/d rev. 12, 1/16 en 27 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features gain digital gain digital gain can be controlled globally by r0x305e (context a) or r0x30c4 (context b). there are also registers that allow individual control over each bayer color (greenr, greenb, red, blue). the format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain setting and 0b00110000 represents a 1.5x gain setting. the step size for yyyyy is 0.03125 while the step size for xxx is 1. therefore to set a gain of 2.09375 one would set digital gain to 01000011. analog gain the ar0130 has a column parallel architecture and therefore has an analog gain stage per column. there are two stages of analog gain, the first stag e can be set to 1x, 2x, 4x or 8x. this is can be set in r0x30b0[5:4](context a) or r0x30b 0[9:8] (context b). the second stage is capable of setting an additional 1x or 1.25x gain which can be set in r0x3ee4[8]. this allows the maximum possible analog gain to be set to 10x. black level correction black level correction is handled automatically by the image sensor. no adjustments are provided except to enable or disable this fe ature. setting r0x30ea[15] disables the auto- matic black level correction. default setting is for automatic black level calibration to be enabled. the automatic black level correction measures the average value of pixels from a set of optically black lines in the image sensor. the pixels are averaged as if they were light- sensitive and passed through the appropriate gain. this line average is then digitally low-pass filtered over many frames to remove temporal noise and random instabilities associated with this measurement. the new filtered average is then compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. if the average is lower than the minimum acceptable level, the offset correc- tion value is increased by a predetermined am ount. if it is above the maximum level, the offset correction value is decreased by a predetermined amount. the high and low thresholds have been calculated to avoid os cillation of the black level from below to above the targeted black level. at high gain, long exposure, and high temperature condi- tions, the performance of this function can degrade. row-wise noise correction row (line)-wise noise correction is handled automatically by the image sensor. no adjustments are provided except to enable or disable this feature. clearing r0x3044[10] disables the row noise correction. default setting is for row noise correction to be enabled. row-wise noise correction is performed by ca lculating an average from a set of optically black pixels at the start of ea ch line and then applying each average to all the active pixels of the line.
ar0130cs/d rev. 12, 1/16 en 28 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features column correction the ar0130 uses column parallel readout ar chitecture to achieve fast frame rate. without any corrections, the cons equence of this architecture is that different column signal paths have slightly different offsets that might show up on the final image as structured fixed pattern noise. ar0130 has column correction circuitry that me asures this offset and removes it from the image before output. this is done by samp ling dark rows containing tied pixels and measuring an offset coefficient per column to be corrected later in the signal path. column correction can be enabled/disabled via r0x30d4[15]. additionally, the number of rows used for this offset coefficient me asurement is set in r0x30d4[3:0]. by default this register is set to 0x7, which means that 8 rows are used. this is the recommended value. other control features regarding column correction can be viewed in the ar0130 register reference. any changes to column correction settings need to be done when the sensor streaming is disabled and the appropriate triggering sequence must be followed as described below. column correction triggering column correction requires a special proced ure to trigger depending on which state the sensor is in. column triggering on startup when streaming the sensor for the first time after power-up, a special sequence needs to be followed to make sure that the column correction coefficients are internally calcu- lated properly. 1. follow proper power up sequen ce for power supplies and clocks 2. apply sequencer settings if needed 3. apply frame timing and pll setti ngs as required by application 4. set analog gain to 1x and low conversion gain 5. enable column correction and settings 6. disable auto re-trigger for change in conversion gain or col_gain, and enable column correction always. (r0x30ba = 0x0008). 7. enable streaming (r0x301a[2] = 1) or drive the trigger pin high. 8. wait 9 frames to settle. (first frame after coming up from standby is internally column correction disabled.) 9. disable streaming (r0x301a[2] = 0) or drive the trigger pin low. after this, the sensor has calculated the pr oper column correction coefficients and the sensor is ready for streaming. any other settings (including gain, integration time and conversion gain etc.) can be done afterwards without affecting column correction. column correction retrigge ring due to mode change since column offsets is sensitive to changes in the analog signal path, such changes require column correction circuitry to be retr iggered for the new path. examples of such mode changes include: horizontal mirror, ve rtical mirror, changes to column correction settings. when such changes take place, the following sequence needs to take place: 1. disable streaming (r0x301a[2]=0) or drive the trigger pin low. 2. enable streaming (r0x301a[2]=1) or drive the trigger pin high. 3. wait 9 frames to settle.
ar0130cs/d rev. 12, 1/16 en 29 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor features note: the above steps are not needed if the sensor is being reset (soft or hard reset) upon the mode change. test patterns the ar0130 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r 0x3070). only one of the test patterns can be enabled at a given point in time by setting the test_pattern_mode register according to table 7. when test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in test_pat- tern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_r ed (r0x3072) for red pixels. note: turn off black level calibration (b lc) when test pattern is enabled. color field when the color field mode is selected, the valu e for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is select ed, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. the first value in each row is 1. table 7: test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color test pattern 2 100% color bar test pattern 3 fade-to-gray color bar test pattern 256 walking 1s test pattern (12-bit)
ar0130cs/d rev. 12, 1/16 en 30 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read/write access to control and status regis- ters within the ar0130. this interface is desi gned to be compatible with the electrical characteristics and transfer protocols of th e two-wire serial in terface specification. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in th e two-wire serial interface specification allow the slave device to drive s clk low; the ar0130 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start an d stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can ge nerate a start conditio n without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indica tes a write, and a ?1? indicates a read. the default slave addresses used by the ar0130 are 0x20 (write address) and 0x21 (read
ar0130cs/d rev. 12, 1/16 en 31 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor two-wire serial register interface address) in accordance with the specification. alternate sl ave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. an alternate slave address can also be programmed through r0x31fc. message byte message bytes are used for sending register ad dresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receip t of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0130cs/d rev. 12, 1/16 en 32 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 20) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 20 shows how the internal register address maintained by the ar0130 is loaded and incremented as the sequence proceeds. figure 20: single read from random location single read from current location this sequence (figure 21) performs a read us ing the current value of the ar0130 internal register address. the master terminates th e read by generating a no-acknowledge bit followed by a stop condition. the figu re shows two independent read sequences. figure 21: single read from current location sequential read, start from random location this sequence (figure 22) starts in the same way as the single read from random loca- tion (figure 20). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 22: sequential read, start from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+ 1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a
ar0130cs/d rev. 12, 1/16 en 33 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor two-wire serial register interface sequential read, start from current location this sequence (figure 23) starts in the same way as the single read from current loca- tion (figure 21). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 23: sequential read, start from current location single write to random location this sequence (figure 24) begins with the master generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 24: single write to random location sequential write, sta rt at random location this sequence (figure 25) starts in the same way as the single write to random location (figure 24). instead of generating a no-acknowl edge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 25: sequential write, start at random location read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+ 1 a a write data slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
ar0130cs/d rev. 12, 1/16 en 34 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor spectral characteristics spectral characteristics figure 26: quantum effici ency C monochrome sensor 0 10 20 30 40 50 60 70 80 90 350 450 550 650 750 850 950 1050 1150 quantum efficiency (% ) wavelength (nm)
ar0130cs/d rev. 12, 1/16 en 35 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor spectral characteristics figure 27: quantum efficiency C color sensor 0 10 20 30 40 50 60 70 80 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 quantum efficiency (%) wavelength (nm) red green blue
ar0130cs/d rev. 12, 1/16 en 36 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specif ications apply to the following conditions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +70 c; output load = 10pf; frequency = 74.25 mhz. two-wire serial register interface the electrical characterist ics of the two-wire serial register interface (s clk , s data ) are shown in figure 28 and table 8. figure 28: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read wa veforms start after read command and register address are issued. s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ar0130cs/d rev. 12, 1/16 en 37 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 20 00). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor extclk = 27 mhz. 4. a device must internally provide a ho ld time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the devi ce does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be me t. this will automatically be the ca se if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specificatio n) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. table 8: two-wire serial bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ?
ar0130cs/d rev. 12, 1/16 en 38 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications i/o timing by default, the ar0130 launches pixel data, fv, and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the rising edge of pixclk. see figure 29 and table 9 below and table 10 on page 39 for i/o timing (ac) characteris- tics. figure 29: i/o timing diagram table 9: i/o timing characteristics (2.8v v dd _io) 1 conditions: f pixclk =74.25mhz (720p60fps) v dd _io=2.8v; slew rate setting = 4 for pixclk; slew rate setting = 7 for parallel ports symbol definition condition min typ max unit f extclk input clock frequency pll enabled 6 50 mhz t extclk input clock period pll enabled 20 166 ns t r input clock rise time 3ns t f input clock fall time 3ns input clock duty cycle 45 50 55 % t jitter 2 input clock jitter at 27 mhz 600 ps t cp extclk to pixclk propagation delay nominal voltages, pll disabled, slew setting =4 12 20 ns t pixclk pixclk frequency 2 6 74.25 ns t rp pixclk rise time slew rate setting = 4 1.60 2.70 7.50 ns t fp pixclk fall time slew rate setting = 4 1.50 2.60 7.20 ns pixclk duty cycle pll enabled 45 50 55 % t pixjitter jitter on pixclk 1ns t pd pixclk to data[11:0] pixclk slew rate = 4 parallel slew rate = 7 -2.5 3.5 ns t pfh pixclk to fv high pixclk slew rate = 4 parallel slew rate = 7 -2.5 0.5 ns t plh pixclk to lv high pixclk slew rate = 4 parallel slew rate = 7 -3.0 0.0 ns data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid
ar0130cs/d rev. 12, 1/16 en 39 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications notes: 1. minimum and maximum values are for the spec limits: 3.1v, -30c and 2.50 v, 70c. all values are taken at the 50% transition point. 2. jitter from pixclk is already taken into acco unt as the data of all the output parameters. notes: 1. minimum and maximum values are for the spec limits: 1.95v, -30c and 1.70v, 70c. all values are taken at the 50% transition point. 2. jitter from pixclk is already taken into acco unt as the data of all the output parameters. t pfl pixclk to fv low pixclk slew rate = 4 parallel slew rate = 7 -2.5 0.5 ns t pll pixclk to lv low pixclk slew rate = 4 parallel slew rate = 7 -3.0 0.0 ns c load output load capacitance 10 pf c in input pin capacitance 2.5 pf table 10: i/o timing characteristics (1.8v v dd _io) 1 conditions: fpixclk=74.25mhz (720p60fps) vdd_io=1.8v; slew rate setting = 4 for pixclk; slew rate setting = 7 for parallel ports symbol definition condition min typ max unit f extclk input clock frequency pll enabled 6 - 50 mhz t extclk input clock period pll enabled 20 - 166 ns t r input clock rise time -3-ns t f input clock fall time -3-ns input clock duty cycle 45 50 55 % t jitter 2 input clock jitter at 27 mhz C 600 C ps t cp extclk to pixclk propagation delay nominal voltages, pll disabled, slew setting =4 12 20 ns f pixclk pixclk frequency 2 674.25mhz t rp pixel rise time slew rate setting = 4 2.50 4.30 7.10 ns t fp pixel fall time slew rate setting = 4 2.20 3.80 6.50 ns pixclk duty cycle pll enabled 45 50 55 % t pixjitter jitter on pixclk 1 ns t pd pixclk to data valid pixclk slew rate = 4 parallel slew rate = 7 C4.5 C 2.0 ns t pfh pixclk to fv high pixclk slew rate = 4 parallel slew rate = 7 C4.0 C C0.5 ns t plh pixclk to lv high pixclk slew rate = 4 parallel slew rate = 7 C4.0 C C0.5 ns t pfl pixclk to fv low pixclk slew rate = 4 parallel slew rate = 7 C4.0 C C0.5 ns t pll pixclk to lv low pixclk slew rate = 4 parallel slew rate = 7 C4.0 C C0.5 ns c load output load capacitance 10 pf c in input pin capacitance 2.5 pf table 9: i/o timing characteristics (2.8v v dd _io) 1 (continued) conditions: f pixclk =74.25mhz (720p60fps) v dd _io=2.8v; slew rate setting = 4 for pixclk; slew rate setting = 7 for parallel ports symbol definition condition min typ max unit
ar0130cs/d rev. 12, 1/16 en 40 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications note: 1. minimum and maximum values are taken at 70 c, 2.5v, and -30 c, 3.1v. the loading used is 10pf. note: 1. minimum and maximum values are taken at 70 c, 2.5v, and -30 c, 3.1v. the loading used is 10pf. note: 1. minimum and maximum values are taken at 70 c, 1.7v, and -30 c, 1.95v. the loading used is 10pf. table 11: i/o rise slew rate (2.8v v dd _io) 1 parallel slew rate conditions min typ max units 7 default 1.50 2.50 3.90 v/ns 6 default 0.98 1.62 2.52 v/ns 5 default 0.71 1.12 1.79 v/ns 4 default 0.52 0.82 1.26 v/ns 3 default 0.37 0.58 0.88 v/ns 2 default 0.26 0.40 0.61 v/ns 1 default 0.17 0.27 0.40 v/ns 0 default 0.10 0.16 0.23 v/ns table 12: i/o fall slew rate (2.8v v dd _io) 1 parallel slew rate conditions min typ max units 7 default 1.40 2.30 3.50 v/ns 6 default 0.97 1.61 2.48 v/ns 5 default 0.73 1.21 1.86 v/ns 4 default 0.54 0.88 1.36 v/ns 3 default 0.39 0.63 0.88 v/ns 2 default 0.27 0.43 0.66 v/ns 1 default 0.18 0.29 0.44 v/ns 0 default 0.11 0.17 0.25 v/ns table 13: i/o rise slew rate (1.8v v dd _io) 1 parallel slew rate conditions min typ max units 7 default 0.57 0.91 1.55 v/ns 6 default 0.39 0.61 1.02 v/ns 5 default 0.29 0.46 0.75 v/ns 4 default 0.22 0.34 0.54 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.17 0.27 v/ns 1 default 0.08 0.11 0.18 v/ns 0 default 0.05 0.07 0.10 v/ns
ar0130cs/d rev. 12, 1/16 en 41 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications note: 1. minimum and maximum values are taken at 70 c, 1.7v, and -30 c, 1.95v. the loading used is 10pf. dc electrical characteristics the dc electrical characteristics are shown in the tables below. table 15: dc electrical characteristics table 14: i/o fall slew rate (1.8v v dd _io) 1 parallel slew rate conditions min typ max units 7 default 0.57 0.92 1.55 v/ns 6 default 0.40 0.64 1.08 v/ns 5 default 0.31 0.50 0.82 v/ns 4 default 0.24 0.38 0.61 v/ns 3 default 0.18 0.27 0.44 v/ns 2 default 0.13 0.19 0.31 v/ns 1 default 0.09 0.13 0.20 v/ns 0 default 0.05 0.08 0.12 v/ns symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs digital supply voltage do not connect. C C C v v ih input high voltage v dd _io*0.7 C C v v il input low voltage C C v dd _io*0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage v dd _io-0.3 C C v v ol output low voltage C C 0.4 v i oh output high current at specified v oh -22 C C ma i ol output low current at specified v ol CC22ma
ar0130cs/d rev. 12, 1/16 en 42 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications caution stresses greater than those listed in table 16 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. notes: 1. exposure to absolute maximum rating cond itions for extended periods may affect reliability. 2. to keep dark current and shot noise artifacts fr om impacting image qualit y, keep operating tem- perature at a minimum. notes: 1. operating currents are measured at the following conditions: v aa =v aa _pix=v dd _io=v dd _pll=2.8v v dd =1.8v pll enabled and pixclk=74.25mhz t a = 25 c table 16: absolute maximum ratings symbol parameter minimum maximum unit v supply power supply voltage (v dd and v aa supplies) C0.3 4.5 v i supply total power supply current C 200 ma i gnd total ground current C 200 ma v in dc input voltage C0.3 v dd _io + 0.3 v v out dc output voltage C0.3 v dd _io + 0.3 v t stg 1 storage temperature C40 +85 c table 17: operating current consumption in parallel output definition condition symbol min typ max unit digital operating current st reaming, 12 80x960 45fps i dd 1 C 40 65 ma i/o digital operating current streaming, 12 80x960 45fps i dd _io C35C ma analog operating current st reaming, 12 80x960 45fps i aa C3055 ma pixel supply current streaming, 1280x960 45fps i aa _pix C 10 15 ma pll supply current stre aming, 1280 x960 45fps i dd _pll C 7 C ma digital operating current streaming, 720p 60fps i dd 1 C40C ma i/o digital operating current streaming, 720p 60fps i dd _io - 35 C ma analog operating current st reaming, 720p 60fps i aa C30C ma pixel supply current streaming, 720p 60fps i aa _pix C 10 15 ma pll supply current streaming, 720p 60fps i dd _pll C 7 C ma
ar0130cs/d rev. 12, 1/16 en 43 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor electrical specifications notes: 1. analog C v aa + v aa _ pix + v dd _ pll 2. digital C v dd + v dd _io + v dd _slvs figure 30: power supply rejection ratio table 18: standby current consumption definition condition symbol min typ max unit hard standby (clock off) analog, 2.8v - C 70 200 a digital, 1.8v - C 640 900 a hard standby (clock on) analog, 2.8v - C 275 C a digital, 1.8v - C 1.55 C ma soft standby (clock off) analog, 2.8v - C 70 200 a digital, 1.8v - C 640 900 a soft standby (clock on) analog, 2.8v - C 275 C a digital, 1.8v - C 1.55 C ma 0 10 20 30 40 50 60 70 1000 10000 100000 1000000 p s r r ? ( d b ) frequency ? (hz) power ? supply ? rejection ? ratio
ar0130cs/d rev. 12, 1/16 en 44 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0130 is shown in figure 31. the avail- able power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 0?10 ? s, turn on v aa and v aa _pix power supply. 3. after 0?10 ? s, turn on v dd power supply. 4. after 0?10 ? s, turn on v dd _io power supply. 5. after the last power supply is stable, enable extclk. 6. assert reset_bar for at least 1ms. 7. wait 150000 extclks (for internal initialization into software standby. 8. configure pll, output, and imag e settings to desired values. 9. wait 1ms for the pll to lock. 10. set streaming mode (r0x301a[2] = 1). figure 31: power up v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs extclk reset_bar t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
ar0130cs/d rev. 12, 1/16 en 45 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor power-on reset and standby timing notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required af ter power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality is sues and will experience high current draw on this supply. 4. for the case where v dd _io is 2.8v and v dd is 1.8v, it is recommended that the minimum time be 5 ? s. table 19: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix 3 t0 0 10 C ? s v aa /v aa _pix to v dd t1 0 10 C ? s v dd to v dd _io t2 0 4 10 C ? s v dd _io to v dd _slvs t3 0 10 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initializat ion t5 150000 C C extclks pll lock time t6 1 C C ms
ar0130cs/d rev. 12, 1/16 en 46 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor power-on reset and standby timing power-down sequence the recommended power-down sequence for the ar0130 is shown in figure 32. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is re ached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs, if used. 4. turn off v dd _io. 5. turn off v dd . 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 32: power down note: t4 is required between power down and next po wer up time; all decoupling caps from regulators must be completely discharged. table 20: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd _io t0 0 C C ? s v dd _io to v dd t1 0 C C ? s v dd to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s pwrdn until next pwrup time t4 100 C C ms v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
ar0130cs/d rev. 12, 1/16 en 47 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor package dimensions package dimensions figure 33: 48 plcc package outline drawing plcc48 11.43x11.43 case 776al issue o date 30 dec 201 4
ar0130cs/d rev. 12, 1/16 en 48 ?semiconductor components industries, llc, 2016. ar0130cs: 1/3-inch cmos digital image sensor package dimensions figure 34: 48 ilcc package outline drawing ilcc48 10x10 case 847ab issue o date 30 dec 201 4
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make change s without further notice to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purp ose, nor does scillc as sume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time . all operating parameters, in cluding typicals must be va lidated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications inte nded to support or sus tain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purch ase or use scillc prod ucts for any such uni ntended or unau thorized applic ation, buyer shall indemnify and hol d scillc and its officer s, employees, subsid iaries, affiliates, and distributors harmless against all claims, costs, damages, and ex penses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportun ity/affirmative ac tion employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. ar0130cs: 1/3-inch cmos digital image sensor package dimensions ar0130cs/d rev. 12, 1/16 en 49 ?semiconductor components industries, llc, 2016 . figure 35: 48 ilcc package outline drawing ilcc48 10x10 case 847ac issue o date 30 dec 201 4

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